LFSR CPU Running Forth

Summary

LFSR CPU running Forth Author: Richard James Howe License: 0BSD / Public Domain Email: mailto:howe.r.j.89@gmail.com Repo: https://github.com/howerj/lfsr-vhdl This project contains a CPU written in VHDL for an FPGA using a Linear Feedback Shift Register (LFSR) instead of a Program Counter, this was sometimes done to save space as a LFSR requires fewer gates than an adder, however on an FPGA it will make very little difference as the units that make an FPGA (Slices/Configurable Logic Blocks) have carry chains in them. The saving would perhaps be more apparent if making the system out of 7400 series ICs, or if laying transistors out by hand. See https://github.com/howerj/lfsr for more information. The system contains a fully working Forth interpreter. The project currently works in simulation (it outputs the startup message "eForth 3.3" with a new line) and accepts input (try typing "words" when the simulation in GHDL is running). Here is an example session of the simulator running: And the VHDL running under GHDL for a limited number of cycles: CPU Resource Utilization The system runs can run at 151.768MHz (on a Spartan-6) according to the timing report. The CPU itself is quite small, here is a cut-down report on the resources consumed for commit 7dc4c9b7e03082364b09540bb2d97105d2858d0b : +------------------------------------------------------------+ | Module | Slices | Slice Reg | LUTs | BRAM/FIFO | BUFG | +------------------------------------------------------------+ | top/ | 3/53 | 9/105 | 1/151 | 0/8 | 1/1 | | +system | 0/27 | 0/47 | 0/85 | 0/8 | 0/0 | | ++bram | 0/0 | 0/0 | 0/0 | 8/8 | 0/0 | | ++cpu | 27/27 | 47/47 | 85/85 | 0/0 | 0/0 | | +uart_rx_0 | 12/12 | 24/24 | 39/39 | 0/0 | 0/0 | | +uart_tx_0 | 11/11 | 25/25 | 26/26 | 0/0 | 0/0 | +------------------------------------------------------------+ No LUTRAM/BUFIO/DSP48A1/BUFR/DCM/PLL_ADV used The above is indicative only as the actual resources used may vary from commit to commit, but also because of the tool ch...