Roughly every two years, the density of transistors that can be fit onto a silicon chip doubles. This is Moore’s Law. Roughly every five years, the cost to build a factory for making such chips doubles, and the number of companies that can do it halves. 25 years ago, there were about 40 such companies and the cost to build a fab was about $2-4 billion. Today, there are either two or three such companies left (depending on your optimism toward Intel) and the cost to build a fab is in excess of $100 billion. Project these trends forward another ten years and you can expect a single factory to cost nearly half a trillion dollars, and the number of companies that can do it should drop to less than one.The plot from Gordon Moore’s original paperThe cutting edge of transistors are “2 nanometer”. Intel has abandoned nanometers as a metric and have begun using terms like 20A, 18A, and 14A, measuring in angstroms (1/10 of a nanometer, or the approximate width of a typical atom). However, these nanometer numbers are entirely fake today. This used to be an objective measure of the width of the gate on a planar transistor, but planar transistors stopped working 15 years ago. Their current substitute, FinFET transistors, have no equivalent feature to measure. The physical feature these numbers once measured no longer exists, but some naming scheme is still needed.The advertised transistor density of modern 2nm nodes is somewhere around 200-250 million transistors per square mm. There are one trillion square nanometers in a square millimeter, and dividing this out this gives us a footprint of 4000-5000 square nanometers per transistor, or roughly a square 60nm on each side. The gate pitch, or minimum distance between transistors, is generally in the range of 30-40nm, and the 60x60nm footprint is a result of geometric constraints on how densely irregular circuits can be packed, leaving unavoidable empty space.The extremely tiny features on a chip are produced via photolithography ...
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