SUS Lang: The SUS Hardware Description Language

Summary

Why SUS? The SUS HDL stands out compared to other HDLs like Verilog or VHDL due to its: ⚡ Latency Counting Timing and pipelining is easier to reason about because the compiler keeps track of them. 🛠️ Made for tinkering The compiler keeps track of many aspects of your hardware design, and displays them in the editor. 🔒 Full Control If you can draw your design as synchronous logic, you can represent it in SUS. 💡 Powerful Metaprogramming SUS allows compile-time code execution to generate LUTs module tree_add #(int WIDTH) { input int[WIDTH] values; output int sum; if WIDTH == 1 { sum = values[0]; } else { gen int HALF_WIDTH = WIDTH / 2; tree_add #(WIDTH: HALF_WIDTH) left; tree_add #(WIDTH: HALF_WIDTH) right; for int i in 0..HALF_WIDTH{ left.values[i] = values[i]; right.values[i] = values[i+HALF_WIDTH]; } if WIDTH % 2 == 0 { reg sum = left.sum + right.sum; } else { reg sum = left.sum + right.sum + values[WIDTH - 1]; } } Core Philosophy The SUS HDL is meant to be a direct competitor to Synthesizeable Verilog and VHDL. Its main goal is to be an intuitive and thin syntax for building netlists, such that traditional synthesis tools can still be used to analyze the resulting hardware. SUS shall impose no paradigm on the hardware designer, such as requiring specific communication protocols or iteration constructs. In other words, SUS is not there to abstract away complexity, but rather to make the inherent complexity of hardware design more manageable. The one restriction SUS does impose over Verilog and VHDL is that it requires the hardware to be synchronous over one or more clocks. Asynchronous hardware is therefore unrepresentable making SUS less suitable for ASIC development. Generative Variables and Types: Can be freely combined, sidestepping any "Dependent Types" headaches. Easy Pipelining: Achieved through an orthogonal construct called "Latency Counting" that doesn't interfere with other features. Separation of Pipelines: Using interfaces to prevent crossing signals wi...