Test Results for AMD Zen 5 by Agner Fog

https://news.ycombinator.com/rss Hits: 13
Summary

I have now finished testing the Zen 5. Thank you to the people who have helped running test scripts for me. My test results for the AMD Zen 5 are impressive. It has a lot of features that increase different aspects of the CPU performance to new levels, never seen before. Most importantly, the instruction fetch rate is increased from 16 to 32 bytes per clock cycle. The 16-bytes fetch rate has been a serious bottleneck in both Intel and AMD processors through many generations. The size of one instruction can be anywhere from 1 to 15 bytes. An AVX512 instruction can be from 6 to 11 bytes. This was a serious bottleneck since the rest of the pipeline could handle four instructions per clock cycle or more in earlier AMD processors as well as Intel processors. Only loops that fit into the micro-op cache could utilize the high throughput. The Zen 5 can execute up to six instructions per clock cycle (rarely eight). Such a high throughput requires careful considerations from the software programmer to avoid long dependency chains. A dependency chain is a situation where each instruction depends on the result of the preceding instruction so that it is impossible to execute more than one instruction at a time. The number of execution units is increased over previous models. There are six integer ALUs, four address generation units, three branch units, four vector ALUs, and two vector read/write units. All common instructions have more than one execution unit to choose between so that it will rarely have to wait for a vacant unit. It is possible to do six simple integer instructions per clock cycle. Vector instructions and floating point instructions can execute at a rate of two vector additions, two vector multiplications, and two vector read or write instructions simultaneously per clock cycle. All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. Integer memory operations can execute at...

First seen: 2025-07-26 19:14

Last seen: 2025-07-27 07:21