Introduction This blog post describes the progress of the first phase of enabling AMD Turin support in coreboot and porting Gigabyte MZ33-AR1 board. The project is funded by NLnet Foundation. The project was inspired by AMD’s efforts to bring open-source firmware for their most recent CPUs. Couple months ago AMD published their CPU initialization code for AMD Turin server processor family on GitHub. The OpenSIL is a new initiative to unify the silicon initialization for AMD platform across multiple firmware frameworks, like EDK2 and coreboot. Following the successful integration of Genoa (Turin’s predecessor) Proof of Concept in coreboot, we are striving for a brand new Turin processor family. The first phase of the project consisted of couple milestones: Milestone a. Turin PSP firmware package Extract APCB from the reference MZ33-AR1 image and add them to mainboard code in coreboot. Integrate support for stitching public Turin PSP blobs in coreboot. Milestone b. Turin SoC skeleton in coreboot Create soc/amd/turin_poc in coreboot, port minimal OpenSIL integration and make sure the tree compiles. Milestone c. MZ33-AR1 mainboard skeleton Add mainboard/gigabyte/mz33-ar1, wire it to the new SoC, enable serial console, and confirm the bootblock executes on hardware. Let’s run through each of them and explain what was done to fulfill the goals. Turin SoC skeleton in coreboot SoC structure is the base of the “world” for building coreboot images for board. It binds the mainboard code with silicon specific drivers and glues all other pieces together. It is usually necessary to have a separate soc directory with relevant source for each new microarchitecture/processor family, as the differences between them may be too significant for reuse. In our case we created the turin_poc SoC based on genoa_poc SoC, as it is the closest SoC to Turin (architecture-wise) and it already integrates OpenSIL drivers. So the easiest way is to simply copy the directory and rename genoa to turin ...
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Last seen: 2025-08-16 02:24