Stealing Debug Pretty Print from Vitis HLS

Summary

Stealing Debug Pretty Print from Vitis HLS I learned that this is the GNU Debugger logo! When working on a high-level synthesis (HLS) hardware design project, I usually start with “C-simulation.” With this type of simulation, I compile my C++ HLS code along with a testbench (typically an int main() function) and run the resulting binary to check if the code is functionally correct. Checking functional correctness involves things like comparing results with a golden model using C++ asserts, or dumping output to a file for further analysis in Python. A good HLS designer also knows C-simulation does have significant limitations. It completely misses many issues that are hardware specific—things you’d catch by running RTL cosimulation after HLS synthesis. But this is another rabbit hole for a different time. Still, C-simulation is considered “fast”: you just recompile your C++ code (Clang is used behind the scenes) and run it. I say “fast” in air quotes because I lied. The Vitis HLS-specific header libraries for things like vendor datatypes and streams can absolutely wreck compile times. Even for a simple C++ HLS design, compile times can balloon past 5 seconds when including these header files, which adds up when trying to iterate quickly. Anyways, C-simulation also lets me debug things in my own development environment instead of the godforsaken Vitis HLS GUI or new Vitis GUI. Rather than using the GUI, I can run the csim_design flow to generate and run the simulation binary all with tcl scripts and my own build scripts as well as have VS Code launch GDB pointing to the generated "csim" binary for my own debugging experience. Even better, if I just want to build the binary and not run it, I can just use the csim_design -setup command instead. This can all be wrapped in Python scripts, makefiles, justfiles, and so on. Anyways, I now have my own slick workflow where I compile my code via the csim_design command (which uses the shipped Clang compiler for Vitis HLS) and r...