Adding a new instruction to RISC-V back end in LLVM

Summary

A compiler is often referred to be a mysterious piece of software. It takes a program written in a high-level language, applies dozens of transformations on it, and then spits out optimized machine code. It sounds like black magic. In this article, however, I would like to provide a counter argument by implementing a new dummy instruction in LLVM, and hopefully demonstrate how surprisingly straightforward it is if you know your way around. Here is our plan: add a new instruction to the RISC-V target; make this instruction available through a feature flag; and finally use and assembler to assemble a program. Every file I mention from now on is assumed to be inside the llvm/lib/Target/RISCV directory unless otherwise specified. I will be using LLVM 20.1, in case you would like to reproduce. The instruction # We will be creating an instruction called foo that takes two operands in registers and stores the result in another register. In RISC-V parlance, this is an R-type (register) instruction. For example, we expect instructions of the form: 1foo x1, x2, x3 R-type instructions in RISC-V are 32-bit wide (as most other instructions) and have the following encoding: The first field is called opcode, is 7-bits wide, and identifies the instruction. We will be using the opcode 0b0001011, also called custom-0, that is reserved in the ISA specification for non-standard instructions. The next field, rd encodes the destination register, which is one of the 32 available general purpose registers r0 through r31. Fields func3 and funct7 serve as complements to the opcode and help further identify which instruction is this. For example, opcodes usually identify a larger class of instructions (i.e. arithmetic and logic instructions) and these fields identify if it is an addition, subtraction, shift, exclusive or, etc. For our purposes here, both will be set to all zeroes. Finally, fields rs1 and rs2 encode the two source operands. Interlude # Before going into the implementation, we ...