Researchers build a RISC-V processor using a 2D semiconductor

Summary

Still, there were some distinct challenges involved with MoS2. In normal silicon, a transistor's threshold voltage can be adjusted by doping the silicon—implanting impurities that change the semiconductor's behavior. But there's no way to implant an impurity in a single molecule. All of the semiconductors of RV32-WUJI are n-type, and their performance can't be adjusted. So the researchers here used two different metals (aluminum and gold) for the wiring and adjusted each transistor's threshold voltages through the choice of wiring, as well as the material the wiring was embedded in. Making chips On the chip level, the researchers experimented with building many individual devices and then used machine learning to identify the optimal combination of wiring and materials that ensured each individual transistor would reside within the needed performance envelope. At the transistor level, the device uses what are called depletion-mode inverters. To build functional circuitry, the researchers built and tested a full suite of 25 logic gates and tested them. Eighteen were functional, and the researchers built the chip using those. They used the longest path through the chip to determine the delay they had to account for, which set an upper limit on clock speed in the kilohertz range. The overall yield when finally making the chip was over 99.9 percent, with a chip-level yield of 99.8 percent. That said, some of the circuitry proved considerably more challenging. The yield on eight-bit registers, for example, was only 71 percent, and that dropped to only seven percent for a 64-bit register (which required 1,152 transistors). The resulting processor involves 5,900 individual transistors and is capable of implementing the full 32-bit version of the RISC-V instruction set, which necessarily means it includes sophisticated circuitry like the RISC-V instruction decoder. At the same time, some aspects are intentionally kept simple; while it can perform the addition of two 32-bit ...