W65C832 in an FPGA

Summary

W65C832 In An FPGA Posted: October 16, 2024 Introduction Back in the 80's, the Western Design Center (WDC) created a 16 bit version of the 6502 CPU called the W65C816. I believe it was created for the Apple IIgs computer, although it was also used in the Super Nintendo. It appears they had a data sheet for a 32 bit version of the chip called the W65C832. I decided to do a Verilog version of it in an FPGA. I updated naken_asm so it has a .65832 directive that allows immediate values for things like lda and such to have a .l modifier so it can do 32 bit values now. The instruction set is able to access 16MB of RAM. The FPGA itself has a small amount of block RAM that this w65c832 core uses as 4k of RAM at the bottom of memory (for zero / direct page), 4k as ROM, and 4k as pages for a Winbond W25Q128J flash chip. More on that further on this page. The Verilog source code is available on GitHub and builds with the regular opensource FPGA tools: yosys, nextpnr-ice40, icepack, and iceFUNprog. I recently added support for the Tang Nano 20k board (should work with the 9k model too) using the same basic set of tools: yosys, nextpnr-himbaechel, gowin_pack, and openFPGAloader. The Makefile shows how they are both built. Hopefully a bigger project will come from this. Joe Davisson created a really wicked graphics demo in assembly with this core along with an XMODEM bootloader so that programs can be uploaded over a UART instead of built into the Verilog: Joe's W65C832 demo. Related Projects @mikekohn.net FPGA: FPGA VGA, Nexys2, Glow In The Dark Memory, Intel 8008, F100-L, RISC-V, x86 / 68000, MIPS, MSP430, PowerPC, W65C832 65C832 The chip itself has 3 registers still: A (8/16/32 bit accumulator) X (8/16/32 bit index x) Y (8/16/32 bit index y) Along with some more internal registers of the 6502 and some newer 65C816 registers: SP (16 bit stack pointer) PC (16 bit program counter) DR (Direct Register - 65C816) DRB (Data Bank Register - 65C816) PRB (Program Bank Register to extend...