Subnanosecond Flash Memory

Summary

Device fabricationThe bottom control gates (5/15 nm Cr/Au) were patterned by e-beam lithography with a bilayer photoresist process followed by deposition of metal by e-beam evaporation on silicon dioxide (300 nm)/silicon substrates. For the flash memory, following the preparation of the bottom gates, an Al2O3 blocking oxide and an HfO2 trap layer were grown by thermal atomic-layer deposition at 250 °C. During the atomic-layer-deposition process, trimethylaluminium and tetrakis(ethylmethylamino)hafnium reacted with water to form Al2O3 and HfO2, respectively. This atomic-layer-deposition process is necessary only for flash fabrication. WSe2, graphene and hBN bulk crystals were purchased from HQ Graphene and the heterostructure of the 2D materials was prepared using mechanical exfoliation and a dry-transfer approach. The hBN flake was first transferred to the bottom gate, and then the thin-body material was transferred onto the hBN flake. The adhesion of the heterostructure on the substrate was improved by heat annealing for more than 2 h at 200 °C under a nitrogen atmosphere. Next, drain–source contacts were patterned by e-beam lithography, and a metal stack (WSe2, 10/12 nm Sb/Pt; graphene, 5/60 nm Cr/Au stack) was deposited using e-beam evaporation. After the standard lift-off approach, devices with the Sb/Pt contact were annealed by the hot plate in the glove box (200 °C, 2 h) to form the alloy. To conduct the sub-1-ns flash memory test, metal wires and pads matched with the radio-frequency probes were patterned by e-beam lithography, and 5/60 nm Cr/Au was deposited by e-beam evaporation.Material characterizationAtomic force microscopy for the devices was measured by a MFP-3D Origin+ (Asylum Research, Oxford Instruments) system. The transmission-electron-microscopy-ready sample was prepared using an in situ focused ion-beam lift-out technique on a Thermo Scientific Helios Eurofins EAG lab G4 HX or UC Dual Beam focused ion-beam/scanning electron microscope. The sampl...